Junction gate field-effect transistors (JFETs, sometimes also referred to as JUGFETs) are widely used as electronically controlled switching structures in wide band-gap semiconductor devices such as silicon carbide (SiC) semiconductor devices. In JFETs a substantially unipolar current flows between a source metallization (source terminal) and a drain metallization (drain terminal) through a semiconducting channel (channel region) controlled by applying an appropriate voltage to a gate metallization (gate terminal) in contact with a gate region forming a pn-junction with the channel. In normally-on JFETs, the channel is “pinched off” by applying a reverse bias voltage to a gate metallization, i.e. a voltage reversely biasing the pn-junction, which is higher than the pinch-off voltage of the JFET.
In lateral JFETs having a lateral channel, the channel is typically defined during manufacturing by a high temperature epitaxial deposition. Using this sophisticated process, the manufactured channel width is mainly determined by the thickness of the epitaxially deposited layer. Typically, a narrow process window is used for the epitaxial deposition to reduce the variability of the pinch-off voltage resulting from the thickness variability. However, this may result in a low yield. The variability of channel width and pinch-off voltage, respectively, of vertical JFETs is mainly determined by lithography variations, in particular CD-variations (critical dimension variations). This typically also results in a trade-off between processing yield and variability of the pinch-off voltage.
For these and other reasons, improvements are needed.